Crossbar-based Nanoelectronic Architectures

The last 40 years have seen an exponential increase in the number of transistors per processor. Along with this increase has been an exponential increase in processor performance. However, now that CMOS scaling has reached the deep submicron range, fundamental physical properties are limiting the further scaling of this technology. Nanoelectronic devices have recently been developed as one possible alternative or complement to CMOS. While these devices offer the potential for circuit densities far exceeding that of CMOS, they also present a new set of challenges. High levels of defects and faults along with a unique bottom-up approach to fabrication are hallmarks of these nascent devices and must be taken into account in order to realize their full potential. In this paper we look at work in the area of building processors that use nanoelectronic crossbar architectures. We examine multiple approaches to two basic issues: organizing devices into a basic computing fabric and ways to map specific functionality onto this computational fabric.